Importance Sampling for SPICE-level Verification of Analog Decoders

Analog circuits for implementing soft decoding algorithms have been proposed and demonstrated by several researchers [1]. Optimization and verification of analog circuits remain difficult because the effects of non-ideal circuit behavior can be difficult or impossible to analyze. Importance sampling permits evaluation of analog designs using precise physical models in SPICE simulations. SPICE provides extremely accurate circuit simulations, but requires large simulation time, making precise error-rate estimates impossible. With importance sampling, the decoder’s performance can be accurately estimated for any SNR with only a few hundred samples. This allows evaluation and optimization of analog decoder designs without the high cost of fabricating and testing an integrated circuit.